1. Field of the Invention
The present invention relates generally to electronic logic circuits, and more particularly to a current-mode logic circuit capable of operating at a high speed and with low power consumption.
2. Description of Related Art
Advancements in the technology of digital computers are coming at the system level via improvement of programming techniques and at the hardware level through improved circuit technology. The logic circuits employed in digital computers may be either voltage-mode or current-mode. Heretofore, the voltage-mode logic such as diode-transistor logic and transistor-transistor logic has been predominant. In the voltage-mode logic, the voltage level of a signal imports determines the content. However, the voltage-mode logic has the inherent delay attendant with transistor saturation, and therefore, has no longer fulfilled the increasing speed requirement of modern digital computers.
Current-mode logic, wherein a logic signal is transmitted through currents, overcomes some of the limitation of the voltage-mode logic. For example, fewer circuit elements and less supply power are required than for the voltage-mode logic. More importantly, increased circuit speed can be obtained in comparison with the voltage-mode logic.
Typically, the current-mode logic includes an emitter-coupled single differential circuit as the primary switch, and an emitter-follower driver is often associated to each output of the differential circuit for driving a succeeding logic gate. Ordinarily, this emitter-follower driver is so very simply constructed with a single transistor connected at its base to a corresponding output of the emitter-coupled single differential circuit and at its emitter to an input of a succeeding logic and also to a voltage supply terminal through a resistor. With this arrangement, a voltage signal appearing across the emitter resistor is supplied to the succeeding logic circuit.
On the other hand, the circuit inevitably has a parasitic capacitive load which includes a wiring capacitance between the output of the emitter-follower and the input of the succeeding logic gate and an input capacitance of the succeeding logic gate. This parasitic capacitive load is charged and discharged every time the emitter-follower transistor is turned on and off. Particularly, when the emitter-follower transistor is turned off, the voltage across the emitter resistor changes with a time constant determined by the resistance of the emitter resistor itself and the capacitance of the parasitic capacitive load. This means that if the parasitic capacitive load is relatively large, the voltage across the emitter resistor will not sharply fall down. Namely, the circuit has a substantial delay time, which is a hindrance in speed-up of the logic circuit.
In order to achieve the speed-up in this circuit structure, one might consider decreasing the resistance of the emitter resistor to decrease the time constant in question. However, the decrease of the emitter-resistance leads to an increase of consumed power of the emitter-follower driver. In addition, the increased power consumption of the circuit will decrease the integration density when it is assembled in integrated circuits.